摘要 |
Embodiments of the invention provide a method, distributed antenna system (50), and components that generate a jitter reduced clock signal from a serial encoded binary data stream transmitted over a communication medium (60, 60a-e, 66). The method comprises receiving a modulated signal that includes the encoded binary data stream and extracting the encoded binary data stream. The method further comprises generating a recovered clock signal (92, 1 12, 206) that is phase locked to the encoded binary data stream, generating an error signal (VERROR) based on a difference between a phase of the encoded binary data stream and the recovered clock signal (92, 112, 206), and integrating the error signal (VERROR) to generate a signal (VCONTROL) to control a voltage controlled oscillator (70, 216, 216a-c, 258). The method further comprises generating a stable recovered clock signal (95, 208) and producing at least one output clock (224) by scaling the stable recovered clock signal (95, 208) frequency. |
申请人 |
ANDREW LLC;MCALLISTER, DONALD;RANSON, CHRIS;PHILLIPS, FRED WILLIAM |
发明人 |
MCALLISTER, DONALD;RANSON, CHRIS;PHILLIPS, FRED WILLIAM |