A DIGITAL PHASE-LOCKED LOOP CLOCK SYSTEM

摘要

A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitallycontrolled oscillator (DCa) including a sigma- delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for accumulating the difference signal over time. The sigma-delta modulator (SDM) may have a control input coupled to the buffer. The adder may have inputs coupled to the (SDM) and a source of an integer control word.