<p>A controller unit (20) outputs a first signal (DQS) and a second signal (DATA) which maintains a phase relationship with the first signal. The second signal (DATA) is input through a FIFO memory (110) of an error detection unit (10) to a memory I/F unit (30). The memory I/F unit (30) performs timing adjustment of the first and second signals (DQS, DATA), outputs to a memory (5), and performs loop-back of the second signal (DATA). A data comparator (125) compares the loop-backed second signal (DATA) with the original second signal (DATA) output from the FIFO memory (110) and corresponding to the loop-backed signal.</p>
