| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of chip size reduction and multiple bits. <P>SOLUTION: A third chip pad line 4C positioned outside of ends of first and second chip pad lines 4A and 4B is aligned on an extension line of the center line between the first chip pad line 4A and the second chip pad line 4B. Therefore, chip pads 4 comprising the third chip pad line 4C can keep longer distance in Y direction to chip pads 6 comprising first and second bonding pad lines 6A and 6B than to chip pads 4 comprising the first and second chip pad lines 4A and 4B. As a result, angles to the Y-direction of bonding wires 7 connecting chip pads 4 to bonding pads 6 can be reduced. <P>COPYRIGHT: (C)2012,JPO&INPIT |
