发明名称 SEMICONDUCTOR DEVICE FAILURE ANALYSIS SYSTEM AND METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a semiconductor device failure analysis system that displays a fail bit map speedily so as to prevent increase in the cost of semiconductor device testing. <P>SOLUTION: A failure analysis system performs mesh splitting of a physical fail bit map, sorts the fail bit map image data of a part of the bit failure area by a contraction ratio, a chip, and a layer, and stores it in a first image data storage area 32. The failure analysis system also sorts the fail bit map image data by a failure mode type, a contraction ratio, a chip, and a layer, and stores it in a second image data storage area 34. Furthermore, the failure analysis system extracts the fail bit map image data from the first image data storage area 32 or the second image data storage area 34, merges it, and displays it on a display part 44, on the basis of instruction from a user for a display format and/or a display area. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012018052(A) 申请公布日期 2012.01.26
申请号 JP20100154968 申请日期 2010.07.07
申请人 TOSHIBA CORP 发明人 KODAMA MASAMI;IIZUKA YOSHIKAZU;YOSHIMURA MASAKI
分类号 G01R31/28;G11C29/40;G11C29/44;H01L21/66 主分类号 G01R31/28
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