<p>Systems and methods are provided for in-DRAM cycle-based levelization. In a multi-rank, multi-lane memory system, an in-DRAM cycle-based levelization mechanism couples to a memory device in a rank and individually controls additive write latency and/or additive read latency for the memory device. The in-DRAM levelization mechanism ensures that a distribution of relative total write or read latencies across the lanes in the rank is substantially similar to that in another rank.</p>
申请公布号
EP2410436(A1)
申请公布日期
2012.01.25
申请号
EP20110184468
申请日期
2008.06.12
申请人
RAMBUS INC.
发明人
CLINE, JULIA, V.M.;HO, EUGENE, C.;STOTT, BRET, G.;WARE, FREDERICK, A.