发明名称 Information processing apparatus, cache memory controlling apparatus, and memory access order assuring method
摘要 According to an aspect of the embodiment, when data on a cache RAM is rewritten in a storage processing of one thread, an determination unit searches a fetch port which holds a request of another thread, checks whether a request exists whose processing is completed, whose instruction is a load type instruction, and whose target address corresponds to a target address in a storage processing. When the corresponding request is detected, the determination unit sets a re-execution request flag to all the entries of the fetch port from the next entry of the entry which holds the oldest request to the entry which holds the detected request. When the processing of the oldest request is executed, a re-execution request unit transfers a re-execution request of an instruction to an instruction control unit for the request held in the entry in which the re-execution request flag is set.
申请公布号 US8103859(B2) 申请公布日期 2012.01.24
申请号 US20090654380 申请日期 2009.12.17
申请人 KIYOTA NAOHIRO;FUJITSU LIMITED 发明人 KIYOTA NAOHIRO
分类号 G06F9/52 主分类号 G06F9/52
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