| 摘要 |
A spacer lithography process for creating negative features such as, for example, cut-lines, or trenches, and holes is provided. The negative spacer lithography process may be utilized along with positive spacer lithography to fabricate electronic devices or the like. In one embodiment, a process is provided for fabricating a 6-transistor Static Random-Access Memory (SRAM) cell or arrays of 6-transistor SRAM cells using only, or at least primarily, positive and negative spacer lithography. |
