发明名称 Combined Single Error Correction/Device Kill Detection Code
摘要 In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.
申请公布号 US2012017135(A1) 申请公布日期 2012.01.19
申请号 US201113246736 申请日期 2011.09.27
申请人 LILLY BRIAN P.;GRIES ROBERT;SUBRAMANIAN SRIDHAR P.;BISWAS SUKALPA;CHEN HAO 发明人 LILLY BRIAN P.;GRIES ROBERT;SUBRAMANIAN SRIDHAR P.;BISWAS SUKALPA;CHEN HAO
分类号 H03M13/09;G06F11/08 主分类号 H03M13/09
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