发明名称 VERIFICATION SUPPORT PROGRAM, VERIFICATION SUPPORT APPARATUS, AND VERIFICATION SUPPORT METHOD
摘要 <P>PROBLEM TO BE SOLVED: To enable a reduction in the period of verification of device operation. <P>SOLUTION: A verification support apparatus 101 detects time t1, the time when packet P3 of transaction T3 is skipped. Subsequently, the verification support apparatus 101 detects time t2, the time of the first transmission of the packet P3 after the time t1 when the packet P3 is skipped. Then, the verification support apparatus 101 computes time d1, the time that elapses from the time t1 when the packet P3 is skipped until the time t2 when the packet P3 is transmitted. The verification support apparatus 101 outputs the computed time d1 as the delay time that occurs for the packet P3, consequent to the skipping of the packet P3. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012015905(A) 申请公布日期 2012.01.19
申请号 JP20100152258 申请日期 2010.07.02
申请人 FUJITSU LTD 发明人 PARISI MATTHEW;IWASHITA HIROAKI
分类号 H04L12/70 主分类号 H04L12/70
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