发明名称 SPECIFYING CIRCUIT LEVEL CONNECTIVITY DURING CIRCUIT DESIGN SYNTHESIS
摘要 Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving custom specifications to the circuit design input, synthesizing high level logic from the circuit design input, placing logic on the circuit design, refining the circuit design and generating a circuit description from the circuit design.
申请公布号 US2012017186(A1) 申请公布日期 2012.01.19
申请号 US20100835780 申请日期 2010.07.14
申请人 AMUNDSON MICHAEL D.;KUCAR DOROTHY;PURI RUCHIR;SZE CHIN NGAI;ZIEGLER MATTHEW M.;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 AMUNDSON MICHAEL D.;KUCAR DOROTHY;PURI RUCHIR;SZE CHIN NGAI;ZIEGLER MATTHEW M.
分类号 G06F17/50 主分类号 G06F17/50
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