发明名称 |
Time-to-digital converter and all-digital phase-locked loop |
摘要 |
<p>A time-to-digital converter (TDC) includes a converter which receives a first signal and a second signal, delays the second signal in phases using a plurality of delay elements which are coupled in series, compares the delayed second signal with the first signal, and outputs a phase error of the second signal with respect to the first signal, a phase frequency detector which receives the first signal, and a third signal from one of the nodes in the plurality of delay elements, and outputs a phase difference between the first signal and the third signal, and a frequency detector which outputs a frequency error of the second signal with respect to the first signal as a digital code using an output signal of the phase frequency detector and the second signal.</p> |
申请公布号 |
EP2192689(B1) |
申请公布日期 |
2012.01.18 |
申请号 |
EP20090177425 |
申请日期 |
2009.11.30 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD.;SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION |
发明人 |
OH, DO-HWAN;CHOO, KYO-JIN;JEONG, DEOG-KYOON |
分类号 |
H03M1/50;H03K5/13;H03K5/131;H03K5/19;H03K5/26;H03L7/085;H03L7/087;H03L7/091 |
主分类号 |
H03M1/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|