发明名称 Error control apparatus
摘要 <p>In an error control apparatus on a receiving side using a hybrid ARQ which combines an error correcting encoding method and an automatic repeat request method, a buffer stores hard decision result data or soft output data instead of soft decision information in order to reduce a memory capacity of the buffer, and re-encodes the data stored to be provided to a combiner. Alternatively, the number of bits of the data stored in the buffer is restricted or a memory included in a decoder is used as an HARQ buffer.</p>
申请公布号 EP2408135(A2) 申请公布日期 2012.01.18
申请号 EP20110178179 申请日期 2003.03.20
申请人 FUJITSU LIMITED 发明人 YANO, TETSUYA;OBUCHI, KAZUHISA
分类号 H04L1/16;G06F11/08;H03M13/00;H03M13/29;H03M13/45;H04L1/00;H04L1/18 主分类号 H04L1/16
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