发明名称 Failure analysis method, failure analysis system, and memory macro system
摘要 Configuration information including number of normal cell areas and number of spare cell areas arranged in a memory macro and a size of each cell area is extracted from circuit design information, and electrical test results of the normal cell areas and the spare cell areas arranged in the memory macro are collected. Arrangement information corresponding to a collection order of the electrical test results is converted to a two-dimensional coordinate value for two-dimensionally displaying the arrangement information corresponding to a collection order of the electrical test results in a unit of cell area in association with a physical layout of a memory cell in the memory macro based on the configuration information. The collected electrical test results are displayed based on the two-dimensional coordinate value so that the normal cell areas and the spare cell areas can be distinguished.
申请公布号 US8099639(B2) 申请公布日期 2012.01.17
申请号 US20090563881 申请日期 2009.09.21
申请人 KODAMA MAMI;KABUSHIKI KAISHA TOSHIBA 发明人 KODAMA MAMI
分类号 G11C29/00 主分类号 G11C29/00
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