APPRATUS FOR RECOVERING CLOCK AND DATA WITH A WIDE RANGE OF FREQUENCY FOR LOW FREQUENCY CIRCUIT

摘要

PURPOSE: An apparatus for recovering a clock and data is provided to reduce the burdens of a PD(Phase Detector) structure and a PD design by maintaining a clock frequency through a loop including the PD. CONSTITUTION: A PLL(Phase locked loop) input circuit unit(110) matches a phase and a frequency between an input signal and a first feedback signal by receiving the first feedback signal of a PPL and the input signal. A band selection circuit unit(120) selects a specific VCO(Voltage Controlled Oscillator) among VCOs(121). A divider(130) controls a frequency of a specific VCO output with a preset division ratio. An interpolator(140) divides the output of the divider into four phases. A data recovery input circuit unit(150) includes a half-rate RD(151), a charge pump(152), and a loop filter(113). A serializer(160) recoveries data by serially rising sampling data.