摘要 |
An apparatus and method is described herein for coupling a processor core of a first type with a co-designed core of a second type. Execution of program code on the first core is monitored and hot sections of the program code are identified. Those hot sections are optimize for execution on the co-designed core, such that upon subsequently encountering those hot sections, the optimized hot sections are executed on the co- designed core. When the co-designed core is executing optimized hot code, the first processor core may be in a low-power state to save power or executing other code in parallel. Furthermore, multiple threads of cold code may be pipelined on the first core, while multiple threads of hot code are pipeline on the co-designed core to achieve maximum performance. |
申请人 |
INTEL CORPORATION;WU, YOUFENG;HU, SHILIANG;BORIN, EDSON;WANG, CHENG, C.;BRETERNITZ, MAURICIO, JR.;LIU, WEI |
发明人 |
WU, YOUFENG;HU, SHILIANG;BORIN, EDSON;WANG, CHENG, C.;BRETERNITZ, MAURICIO, JR.;LIU, WEI |