Random number generator for cryptographic application, has sample and holding circuit that scans switching states of cascaded ring oscillators for generation of random bits

摘要

The random number generator (1) formed by application specific integrated circuit (ASIC) or field programmable gate array (FPGA) has several cascaded ring oscillators (2-1,2-2) and a sample and holding circuit (3). The sample and holding circuit scans switching states of oscillators for generation of random bits. The oscillator has a cascading gate such as exclusive OR (XOR) gate or exclusive NOT-OR (XNOR) gate. The cascading gate of one oscillator is linked to that of next oscillator so that a nonlinear mixer is formed to mix the oscillation signals of cascaded ring oscillators. An independent claim is included for method for generation of random bits.