摘要 |
Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit. In other embodiments, the current drawn by a reference array, where a high voltage is applied to the array with all wordlines non-selected, is compared to the current drawn by an array where the high voltage is applied and one or more selected wordlines. In these current based embodiments, the reference array can be a different array, or the same array as that one selected for testing. |
申请人 |
SANDISK TECHNOLOGIES INC.;LI, YAN;LEE, DANA;HUYNH, JONATHAN H.;PAN, FENG;POPURI, VISWAKIRAN;CAZZANIGA, MARCO |
发明人 |
LI, YAN;LEE, DANA;HUYNH, JONATHAN H.;PAN, FENG;POPURI, VISWAKIRAN;CAZZANIGA, MARCO |