发明名称 |
MEMORY DEVICES AND METHODS HAVING MULTIPLE ADDRESS ACCESSES IN SAME CYCLE |
摘要 |
A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port configured to receive addresses on falling and rising edges of a timing clock, each address corresponding to locations in different banks; and at least two read/write data ports configured to receive write data for storage in one of the banks, and output read data from one of the banks. |
申请公布号 |
WO2012006609(A2) |
申请公布日期 |
2012.01.12 |
申请号 |
WO2011US43481 |
申请日期 |
2011.07.09 |
申请人 |
CYPRESS SEMICONDUCTOR CORPORATION;MAHESHWARI, DINESH |
发明人 |
MAHESHWARI, DINESH |
分类号 |
G11C7/10;G11C7/22;G11C11/413 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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