| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a dummy pattern optimized for both CMP measures and short time optical annealing measures almost without effort to design. <P>SOLUTION: In the semiconductor integrated circuit device 1 having memory macro areas 10 and function circuit areas 20 on a substrate, a dummy pattern area 40 including a dummy pattern 41 is arranged between the function circuit areas 20, and between the memory macro area 10 and function circuit area 20. The dummy pattern 41 is a pattern equivalent to the diffusion layers 12, 13 and the gate electrode 14 of a memory cell pattern 11 in a memory cell array area. Area ratio of dummy diffusion layers 42, 43 and a dummy gate electrode 44 in the dummy pattern area 40 is equal to or higher than that of the diffusion layers 12, 13 and the gate electrode 14 in the memory cell array area. <P>COPYRIGHT: (C)2012,JPO&INPIT |
