发明名称 LAYOUT DESIGN FOR HIGH POWER, GALLIUM NITRIDE BASED FET
摘要 <P>PROBLEM TO BE SOLVED: To provide an FET. <P>SOLUTION: The FET includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer. Source, gate and drain electrodes are located over the barrier layer and extend in a longitudinal direction thereon. A portion of the channel and barrier layers form a mesa extending in the longitudinal direction and the source and drain electrodes extend beyond an edge of the mesa. The gate electrodes extend along an edge sidewall of the mesa. A conductive source interconnect is disposed over the barrier layer and have a first end electrically connected to the source electrode. A first dielectric layer is disposed over the buffer layer and over the source interconnect. A gate via is formed in the first dielectric layer. A conductive gate node extends along the buffer layer and electrically connects to the portion of the gate electrode extending along the sidewall of the mesa. A gate pad is disposed on the first dielectric layer adjacent the mesa. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012009863(A) 申请公布日期 2012.01.12
申请号 JP20110139298 申请日期 2011.06.23
申请人 POWER INTEGRATIONS INC 发明人 LINLIN LIU;MILAN POFFLEY STITCH;BORIS PERES
分类号 H01L27/095;H01L21/338;H01L21/822;H01L27/04;H01L29/778;H01L29/812 主分类号 H01L27/095
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