| 摘要 |
<P>PROBLEM TO BE SOLVED: To easily handle a filter circuit for simultaneously processing a plurality of signal in a predetermined cycle by arranging phases of output data. <P>SOLUTION: A delay adjustment circuit is provided, which delays each signal such that the sum total of delays of a plurality of signals outputted from a one-stage or multistage filter circuit is a multiple of a simultaneous processing number. The delay adjustment circuit is installed at a post stage of the multistage filter circuit, and changes the number of delays in accordance with a change in the simultaneous processing number. <P>COPYRIGHT: (C)2012,JPO&INPIT |
