发明名称 Multi-bus structure for optimizing system performance of a serial buffer
摘要 A serial buffer having a parser and multiple parallel processing paths is provided. The parser receives incoming packets, determines the type of each packet, and then routes each packet to a processing path that corresponds with the determined packet type. Packet types may include blocking priority packets (which implement bus slave operations), non-blocking priority packets (which access on-chip resources of the serial buffer) and data packets (which implement bus master operations). Because the different packet types are processed on parallel processing paths, the processing of one packet type does not interfere with the processing of other packet types. As a result, blocking conditions within the serial buffer are minimized.
申请公布号 US8094677(B2) 申请公布日期 2012.01.10
申请号 US20070679824 申请日期 2007.02.27
申请人 JUAN STEVE;WANG CHI-LIE;CHEN MING-SHIUNG;INTEGRATED DEVICE TECHNOLOGY, INC. 发明人 JUAN STEVE;WANG CHI-LIE;CHEN MING-SHIUNG
分类号 H04J3/16 主分类号 H04J3/16
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