发明名称 OUTPUT ENABLE SIGNAL GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY
摘要 PURPOSE: An output enable signal generation circuit of a semiconductor memory is provided to secure the activation and inactivation of a section signal by dividing circuit configuration of determining the activation and inactivation of the section signal. CONSTITUTION: In an output enable signal generation circuit of a semiconductor memory, a latency signal generating unit(200) generates a latency signal. The latency signal defines the activation timing of a data output enable signal. A data output enable signal generator(400) adjusts the activation timing and inactivation timing of the data output enable signal. A latency signal generating unit comprises a plurality of latency signal generating units(210~260) The latency signal generating unit comprises a selecting unit(270) which selects one reserved latency signal.
申请公布号 KR20120003241(A) 申请公布日期 2012.01.10
申请号 KR20100063998 申请日期 2010.07.02
申请人 HYNIX SEMICONDUCTOR INC. 发明人 BYUN, HEE JIN
分类号 G11C7/10;G11C7/20;G11C7/22 主分类号 G11C7/10
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