Methods and apparatus for interfacing between a host processor and a coprocessor

摘要

An interface to transfer data between a host processor and an external coprocessor is provided. The interface may operate in several write modes, in which in a first write mode the write operation is transferred across the interface in two clock cycles and in a second write mode the write operation is transferred across the interface in a single clock cycle. The interface can perform a first read operation initiated by the host processor and a second read operation initiated by the external coprocessor. The interface can include buffers to store read and write operations and clock gates to selectively gate off clock signals provided to the buffers to synchronize transfer of data into and out of the buffers. A selectable priority scheme can be modified to select between priorities that control a preference in transferring operations over the interface when both read and write operations are queued for transfer.