发明名称 Memory system and method
摘要 In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.
申请公布号 US8095747(B2) 申请公布日期 2012.01.10
申请号 US20080239532 申请日期 2008.09.26
申请人 BARBARA BRUCE;LI GABRIEL;TRAN THINH;TZOU JOSEPH;CYPRESS SEMICONDUCTOR CORPORATION 发明人 BARBARA BRUCE;LI GABRIEL;TRAN THINH;TZOU JOSEPH
分类号 G06F12/00 主分类号 G06F12/00
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