| 摘要 |
AΔΣADC is provided that is capable of suppressing increase of a circuit scale without losing noise shaping function even when a switching speed of a switch for performing time-division process is lower than a sampling rate of theΔΣADC. For a code values provided by a comparator (105), theΔΣADC (100) has a first storage section (106-1) and a second storage section (106-2) respectively for signal sequences (a first signal sequence and a second signal sequence) constituting a time-divisionally combined signal. Then, one of the two storage sections (i.e. the first storage section (106-1) and the second storage section (106-2)) that corresponds to a branch selection signal is configured to store the code value obtained from the comparator (105). On the other hand, one of the two storage sections (i.e. the first storage section (106-1) and the second storage section (106-2)) that is not the storage section corresponding to the branch selection signal is configured to hold the already stored code value.
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