| 摘要 |
<p>An input circuit (20) includes an interface (26) structured to output a logic signal (28) from an alternating current signal (22) of a pair of elongated conductors (24). A load (30) is switchable to the elongated conductors. A processor (32) outputs (35) a control signal (34) to switch the load to the elongated conductors asynchronously with respect to the alternating current signal for a first predetermined time, inputs (36) the logic signal, determines (158,160,162,164) if the input logic signal is active a plurality of times during the first predetermined time and responsively sets a first state of the alternating current signal, and, otherwise, sets an opposite second state of the alternating current signal, and delays (178) for a second predetermined time, which is longer than the first predetermined time, for the opposite second state before repeating the output, and, otherwise, delays (172) for a third predetermined time, which is longer than the second predetermined time, for the first state before repeating the output.</p> |
