发明名称 |
Clock domain partitioning of programmable integrated circuits |
摘要 |
A computer-implemented method of partitioning a circuit design into clock domains for implementation within a programmable integrated circuit (IC) can include storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of constraints regulate placement of components to different clock regions of the programmable IC. The method can include storing an objective function and determining a result indicating whether a feasible solution exists for clock domain partitioning of the circuit design by minimizing the objective function subject to the plurality of constraints. The result can be output. |
申请公布号 |
US8091060(B1) |
申请公布日期 |
2012.01.03 |
申请号 |
US20090368435 |
申请日期 |
2009.02.10 |
申请人 |
TOM MARVIN;DASASATHYAN SRINIVASAN;XILINX, INC. |
发明人 |
TOM MARVIN;DASASATHYAN SRINIVASAN |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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