发明名称 Method for evaluating SOI wafer
摘要 The present invention relates to a method for evaluating the SOI wafer in a method for evaluating an SOI wafer in which a sheet resistance of a buried diffusion layer of an SOI wafer that has at least an SOI layer on an insulator layer and has a buried diffusion layer whose impurity concentration is higher than other region of the SOI layer in an interface area with the insulator layer of the SOI layer is evaluated, the method including the steps of measuring a sheet resistance of the whole SOI layer or the whole SOI wafer, and estimating the sheet resistance of the buried diffusion layer by assuming respective layers that compose the SOI wafer to be resistors connected in parallel and converting the measured result of the sheet resistance measurement. As a result of this, there is provided a method for evaluating the SOI wafer that can directly measure the SOI wafer itself to be the product to thereby evaluate the sheet resistance of the buried diffusion layer thereof, without fabricating a monitor wafer.
申请公布号 US8089274(B2) 申请公布日期 2012.01.03
申请号 US20070227687 申请日期 2007.05.10
申请人 YOSHIDA KAZUHIKO;SHIN-ETSU HANDOTAI CO., LTD. 发明人 YOSHIDA KAZUHIKO
分类号 G01R33/14;G01B7/06;G01R31/26 主分类号 G01R33/14
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