发明名称 INTERLOCK CIRCUIT AND INTERLOCK SYSTEM INCLUDING THE SAME
摘要 PURPOSE: An interlock circuit and an interlock system including the same are provided to suppress signal which is inputted at the same time by attenuating input and output at the same timing. CONSTITUTION: In an interlock circuit and an interlock system including the same, an input delay part(100) delays a plurality of input signals. The input delay part provides a plurality of delay input signals. The input delay part supplies a plurality of exclusion input signals. An suppression output unit(200) offers a plurality of output signals. A plurality of output signals is not activated at the same time.
申请公布号 KR20110139958(A) 申请公布日期 2011.12.30
申请号 KR20100060098 申请日期 2010.06.24
申请人 FAIRCHILD KOREA SEMICONDUCTOR LTD. 发明人 LEE, JUNG HO;KANG, EUN CHUL;OH, WON HI
分类号 H03K5/135;G06F3/06;H03K19/21 主分类号 H03K5/135
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