发明名称 |
ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM |
摘要 |
Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure. |
申请公布号 |
US2011320914(A1) |
申请公布日期 |
2011.12.29 |
申请号 |
US20100822503 |
申请日期 |
2010.06.24 |
申请人 |
ALVES LUIZ C.;GOWER KEVIN C.;GOWER LISA C.;LASTRAS-MONTANO LUIS A.;MEANEY PATRICK J.;STEPHENS ELDEE;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ALVES LUIZ C.;GOWER KEVIN C.;GOWER LISA C.;LASTRAS-MONTANO LUIS A.;MEANEY PATRICK J.;STEPHENS ELDEE |
分类号 |
G06F11/10 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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地址 |
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