SRAM MEMORY CELL BASED ON TRANSISTORS OF INCREASED EFFECTIVE GATE WIDTH AND PRODUCTION PROCESS

摘要

The SRAM memory cell is equipped with two access transistors and two inverters each comprising two transistors. An access transistor is associated with an inverter. Each transistor comprises a semiconductor zone (2) that protrudes from a semiconductor layer (5). The protrusion comprises a main wall (2a) and a sidewall (2b). Each transistor comprises a gate electrode (3', 3") separated from the semiconductor zone (2) by a gate insulator. The gate electrode (3', 3") covers the main wall (2a) of the protruding zone (2) and partially covers the sidewall (2b) of the protruding zone to a covering depth. The covering depth of the sidewalls is different between the two transistors (6a) of the inverter and is also different from the covering depth of the access transistor.