发明名称 |
MULTI-PHASE CLOCK GENERATION |
摘要 |
An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay line delaying the first intermediate signal by a first delay amount; a second delay line delaying the first intermediate signal by a second delay amount; a third delay line delaying the second intermediate signal by a third delay amount; and a fourth delay line delaying the second intermediate signal by a fourth delay amount. The apparatus also includes a closed feedback loop for detecting and adjusting the second and fourth delay amount. |
申请公布号 |
US2011316599(A1) |
申请公布日期 |
2011.12.29 |
申请号 |
US201113227294 |
申请日期 |
2011.09.07 |
申请人 |
KWAK JONGTAE;MICRON TECHNOLOGY, INC. |
发明人 |
KWAK JONGTAE |
分类号 |
H03L7/097;H03K5/15 |
主分类号 |
H03L7/097 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|