GRID-CONTROL PN FIELD EFFECT TRANSISTOR AND CONTROLLING METHOD THEREOF
摘要
<p>A grid-control positive-negative (PN) field effect transistor (200) is provided. The grid-control PN field effect transistor (200) includes a semiconductor substrate region (203), a source region (201) and a drain region (202) located on a left side and a right side of the substrate region (203), grid regions (206,207) located on an upper side and a lower side of the substrate region (203). The grid-control PN field effect transistor (200) reduces leak current and simultaneously increases driving current, thus increases chip performance without increasing power consumption of the chip. A controlling method of the grid-control PN field effect transistor (200) is also provided.</p>
