发明名称 |
JAM LATCH FOR LATCHING MEMORY ARRAY OUTPUT DATA |
摘要 |
A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation device that selectively decouples the feedback inverter from a power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the power supply rail coincides with resetting the data node to the first logic state; and a margin test device that selectively increases pull down strength of the feedback inverter. |
申请公布号 |
US2011317496(A1) |
申请公布日期 |
2011.12.29 |
申请号 |
US20100822038 |
申请日期 |
2010.06.23 |
申请人 |
BUNCE PAUL A.;DAVIS JOHN D.;HENDERSON DIANA M.;VORA JIGAR;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BUNCE PAUL A.;DAVIS JOHN D.;HENDERSON DIANA M.;VORA JIGAR |
分类号 |
G11C7/10 |
主分类号 |
G11C7/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|