发明名称 Integrated Circuit Arrangement For Test Inputs
摘要 An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.
申请公布号 US2011320898(A1) 申请公布日期 2011.12.29
申请号 US20100822287 申请日期 2010.06.24
申请人 BAUR ULRICH;CURLEY LAWRENCE D.;FRISHMUTH RONALD J.;LUDEWIG RALF;TONG CHING L.;WEBEL TOBIAS;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BAUR ULRICH;CURLEY LAWRENCE D.;FRISHMUTH RONALD J.;LUDEWIG RALF;TONG CHING L.;WEBEL TOBIAS
分类号 G01R31/3177;G06F11/25 主分类号 G01R31/3177
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