发明名称 DYNAMIC TRAILING EDGE LATENCY ABSORPTION FOR FETCH DATA FORWARDED FROM A SHARED DATA/CONTROL INTERFACE
摘要 A computer-implemented method for managing data transfer in a multi-level memory hierarchy that includes receiving a fetch request for allocation of data in a higher level memory, determining whether a data bus between the higher level memory and a lower level memory is available, bypassing an intervening memory between the higher level memory and the lower level memory when it is determined that the data bus is available, and transferring the requested data directly from the higher level memory to the lower level memory.
申请公布号 US2011320721(A1) 申请公布日期 2011.12.29
申请号 US20100822884 申请日期 2010.06.24
申请人 BERGER DEANNA POSTLES DUNN;FEE MICHAEL;O'NEILL, JR. ARTHUR J.;SONNELITTER, III ROBERT J.;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BERGER DEANNA POSTLES DUNN;FEE MICHAEL;O'NEILL, JR. ARTHUR J.;SONNELITTER, III ROBERT J.
分类号 G06F12/08;G06F12/00 主分类号 G06F12/08
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