发明名称 BUFFER-AWARE ROUTING IN INTEGRATED CIRCUIT DESIGN
摘要 A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit includes buffers and wires. A route is received from a set of routes. The route couples a first point in the circuit to a second point in the circuit and including at least one buffer between the first point and the second point. A determination is made whether the route violates a set of hard constraints for a part of the circuit, where the set of hard constraints includes a reach length constraint. In response to the route not violating any hard constraint in the set of hard constraints, the route is selected as a buffer-aware routing solution between the first and the second points in the circuit.
申请公布号 US2011320992(A1) 申请公布日期 2011.12.29
申请号 US20100823232 申请日期 2010.06.25
申请人 ALPERT CHUCK;LI ZHUO;MOFFITT MICHAEL DAVID;SZE CHIN NGAI;VILLARRUBIA PAUL G.;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ALPERT CHUCK;LI ZHUO;MOFFITT MICHAEL DAVID;SZE CHIN NGAI;VILLARRUBIA PAUL G.
分类号 G06F17/50 主分类号 G06F17/50
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