发明名称 |
VERIFICATION OF PROCESSOR ARCHITECTURES ALLOWING FOR SELF MODIFYING CODE |
摘要 |
A verification operation including generating a predefined instruction, initializing a relevant self modifying code (SMC) target memory location to form an SMC trap, binding the SMC trap to the predefined instruction to form an SMC trap source and propagating initialization of instruction code into the SMC trap source.
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申请公布号 |
US2011320784(A1) |
申请公布日期 |
2011.12.29 |
申请号 |
US20100822553 |
申请日期 |
2010.06.24 |
申请人 |
ALMOG ELI;KRYGOWSKI CHRISTOPHER A.;MORIMOTO YUGI;RIMON MICHAL;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ALMOG ELI;KRYGOWSKI CHRISTOPHER A.;MORIMOTO YUGI;RIMON MICHAL |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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