发明名称 |
G-ODLAT On-die Logic Analyzer Trigger with Parallel Vector Finite State Machine |
摘要 |
An apparatus for debugging internal signals of integrated circuits is presented. In one embodiment, the apparatus comprises a number of vector registers associated with states of a state machine. A group of registers, associated with a state of the state machine, comprises a mask register an arm register. A comparator compares debug data with contents of the mask register and the arm register to determine a comparison result to be stored in one or more bit positions of the vector register. The apparatus further comprises a triggering logic unit to determine whether or not to trigger a fire event based on the vector registers. |
申请公布号 |
US2011320893(A1) |
申请公布日期 |
2011.12.29 |
申请号 |
US20100823044 |
申请日期 |
2010.06.24 |
申请人 |
KURTS TSVIKA;SKABA DANIEL;ISRAELI MICHAEL;SAMOELOV ITAI;MANDELBLAT JULIUS |
发明人 |
KURTS TSVIKA;SKABA DANIEL;ISRAELI MICHAEL;SAMOELOV ITAI;MANDELBLAT JULIUS |
分类号 |
G01R31/3177;G06F11/25 |
主分类号 |
G01R31/3177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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