| 摘要 |
A sub-stage (212) for a charge pump (200) having a first and second phase of operation. The sub-stage (212) comprising a dc input pin (222); a dc output pin (220); a first rf input pin (202) configured to receive a first differential signal; and a second rf input pin (204) configured to receive a second differential signal. The sub-stage (212) further comprising a first transistor (224) having a first, second and third terminal, wherein a current channel is provided between the first and second terminal of the transistor (224); and a second transistor (226) having a first, second and third terminal, wherein a current channel is provided between the first and second terminal of the transistor (226). The first terminal of the first transistor (224) is connected to the dc input pin (222), the second terminal of the first transistor (224) is connected to the first terminal of the second transistor (226), and the second terminal of the second transistor (226) is connected to the dc output pin (220). The first rf input pin (202) is coupled to the second terminal of the first transistor (224) and the first terminal of the second transistor (226), such that the current channel of the first transistor (224) conducts signalling received at the first rf input pin (202) during the first phase of operation, and the current channel of the second transistor (226) conducts signalling received at the first rf input pin (202) during the second phase of operation. The sub-stage further comprising a first bias voltage source (232) and a second bias voltage source (234); wherein the third terminal of the first transistor (224) is configured to receive a second differential signal from the second rf input pin (204) and a first offset voltage signal from the first bias voltage source (232); and the third terminal of the second transistor (226) is configured to receive a second differential signal from the second rf input pin (204) and a second offset voltage signal from the second bias voltage source (234). |
