发明名称 |
Generation of a low jitter clock signal |
摘要 |
Systems and methods for generation of a low jitter clock signal for wireless circuits are disclosed. In an implementation, the system includes a wireless circuit powered by a first power supply and a low jitter clock (LJC) generator powered by a second power supply. The LJC generator provides at least one clock signal to the wireless circuit. The system further includes an LJC driver circuit including a clock buffer powered by the first power supply and a receive buffer powered by the second power supply. |
申请公布号 |
US8085080(B2) |
申请公布日期 |
2011.12.27 |
申请号 |
US20100714150 |
申请日期 |
2010.02.26 |
申请人 |
SRIDHARAN SRINATH;GANTI RAMKISHORE;GUYARD PATRICK;ST-ERICSSON SA;ST-ERICSSON INDIA PVT. LTD. |
发明人 |
SRIDHARAN SRINATH;GANTI RAMKISHORE;GUYARD PATRICK |
分类号 |
H03K17/16 |
主分类号 |
H03K17/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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