发明名称 Transceiver with latency alignment circuitry
摘要 In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.
申请公布号 US8086812(B2) 申请公布日期 2011.12.27
申请号 US20060465230 申请日期 2006.08.17
申请人 DONNELLY KEVIN;JOHNSON MARK;TRAN CHANH;DILLON JOHN B.;DILLON, LEGAL REPRESENTATIVE NANCY D.;RAMBUS INC. 发明人 DONNELLY KEVIN;JOHNSON MARK;TRAN CHANH;DILLON JOHN B.;DILLON, LEGAL REPRESENTATIVE NANCY D.
分类号 G06F12/00;G06F13/40 主分类号 G06F12/00
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