| 发明名称 |
System for bitcell and column testing in SRAM |
| 摘要 |
A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read. |
| 申请公布号 |
US8085580(B2) |
申请公布日期 |
2011.12.27 |
| 申请号 |
US20100819393 |
申请日期 |
2010.06.21 |
| 申请人 |
MEHTA ASWIN N.;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
MEHTA ASWIN N. |
| 分类号 |
G11C11/00 |
主分类号 |
G11C11/00 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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