发明名称 |
Loading data to vector renamed register from across multiple cache lines |
摘要 |
A load instruction that accesses data cache may be off natural alignment, which causes a cache line crossing to complete the access. The illustrative embodiments provide a mechanism for loading data across multiple cache lines without the need for an accumulation register or collection point for partial data access from a first cache line while waiting for a second cache line to be accessed. Because the accesses to separate cache lines are concatenated within the vector rename register without the need for an accumulator, an off-alignment load instruction is completely pipeline-able and flushable with no cleanup consequences. |
申请公布号 |
US8086801(B2) |
申请公布日期 |
2011.12.27 |
申请号 |
US20090420118 |
申请日期 |
2009.04.08 |
申请人 |
HRUSECKY DAVID A.;RAY DAVID S.;RONCHETTI BRUCE J.;TUNG SHIH-HSIUNG S.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
HRUSECKY DAVID A.;RAY DAVID S.;RONCHETTI BRUCE J.;TUNG SHIH-HSIUNG S. |
分类号 |
G06F13/00 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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