发明名称 |
Automatic clock synchronization and distribution circuit for counter clock flow pipelined systems |
摘要 |
A clock synchronization buffer for a counter clock flow pipelined circuit including a cascade of processing modules that receive data from a previous module and provide output results to a following module. The clock synchronization buffer receives a clock input signal and provides clock signals to a local processing module and to the next pipeline stage. The clock synchronization buffer includes a selectable delay stage that receives a clock input signal and a delay select signal and outputs a clock signal having a selected delay. An amplifier connected to the selectable delay stage provides the delayed clock signal to a local processing module that corresponds to the clock synchronization buffer circuit. An inverting amplifier connected to the selectable delay stage provides the delayed clock signal to the next pipeline stage. A clock synchronization controller synchronizes the phases of reference clock input and synchronized clock input signals. |
申请公布号 |
US8085817(B1) |
申请公布日期 |
2011.12.27 |
申请号 |
US20090580479 |
申请日期 |
2009.10.16 |
申请人 |
FOUTS DOUGLAS JAI;LUKE BRIAN LEE;THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE NAVY |
发明人 |
FOUTS DOUGLAS JAI;LUKE BRIAN LEE |
分类号 |
H04J3/06 |
主分类号 |
H04J3/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|