| 摘要 |
PURPOSE: A duty cycle correction process in a delay locked loop is provided to use a closed loop clock circuit, thereby correcting a duty cycle error with respect to a different period signal and a received or generated clock. CONSTITUTION: A device(110) stores data in a plurality of memories(120). The device includes a memory interface(115) connected to the memory through a data line(125). The memory interface provides a clock, address, and control signal to the memory on a line(117). The line is terminated by a termination(130). A clock signal provided on the line is a single-ended signal or differential signal. The clock signal is transferred to the memory by the memory interface. A clock line is terminated by the termination.
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