发明名称 PROCESSOR SYSTEM USING SYNCHRONOUS DYNAMIC MEMORY
摘要 A processor system including: a processor having a processor core and a controller core; and a plurality of synchronous memory chips, wherein the processor and the plurality of synchronous memory chips are connected via an external bus; wherein the processor core and the controller core are connected via an internal bus; wherein the plurality of synchronous memory chips are operated according to a clock signal; wherein the controller core comprises a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.
申请公布号 US2011314213(A1) 申请公布日期 2011.12.22
申请号 US201113008189 申请日期 2011.01.18
申请人 UCHIYAMA KUNIO;NISHII OSAMU 发明人 UCHIYAMA KUNIO;NISHII OSAMU
分类号 G06F12/00;G06F15/78;G11C7/10;G11C8/12;G11C8/18;H04N7/26;H04N7/50 主分类号 G06F12/00
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