RESISTANCE-CHANGE MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a cell array structure that is capable of reducing the unit area per cell and preventing a decrease in yield in wiring processing.

SOLUTION: In a memory cell array 1 a memory cell pair comprises two memory cells in which word lines WL are arranged adjacently. The two memory cells share a bit line contact BLC. All memory cell pairs connected to two adjacent bit lines are connected to corresponding source lines SL via an individual source line contact SLC. The source lines SL are formed of a wiring layer upper than the bit lines BL at a larger pitch than that of bit lines BL.

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